Silicon Launchpad &
Academic Foundry Alliance
Democratizing commercial wafer fabrication in India. INDNIX opens its Haringhata Mega-Fab cleanrooms to early-stage fabless startups for direct prototype fabrication, and to universities and research institutes for joint R&D and student training.
What INDNIX Provides to Semiconductor Startups
Overcoming the prohibitive multi-million dollar barrier to tape-out. We offer low-cost multi-project wafer runs, verified PDKs, and advanced packaging under one roof.
Multi-Project Wafer (MPW) Shuttles
Share wafer mask costs across multiple design teams. Regularly scheduled shuttle runs in 28nm, 65nm, and 180nm CMOS, as well as GaN/SiC power nodes.
- 10 to 100 prototype packaged dies
- Standard die sizes: 1x1mm to 10x10mm
- Guaranteed turn-around of 8–12 weeks
Verified PDKs & EDA Tool Support
Complete Process Design Kits (PDKs) compatible with Cadence, Synopsys, and Siemens EDA toolflows, including SPICE models, DRC, and LVS decks.
- Comprehensive Design Rule Manuals (DRM)
- Pre-tapeout tape-in DRC verification check
- Open-source toolflow support for academic startups
Packaging, OSAT & Lab Testing
End-to-end back-end packaging (QFN, BGA, Flip-Chip, WLP) and automated test equipment (ATE) verification in our state-of-the-art cleanroom.
- High-frequency RF & mixed-signal probing
- Thermal shock, HTOL, and reliability testing
- Surface mount assembly (SMT) for evaluation boards
5-Step Startup Onboarding Roadmap
From initial NDA execution to final packaged silicon delivery at your engineering desk.
Registration & NDA
Submit company profile below. Sign mutual non-disclosure agreement protecting 100% of your IP.
Process Review
Joint technical review with INDNIX fab engineers to select optimal node (CMOS vs GaN/SiC) and shuttle schedule.
PDK & Tape-Out
Receive complete foundry PDKs, run DRC/LVS, and submit final GDSII/OASIS design files by shuttle cut-off.
Wafer Fab & Dicing
Precision cleanroom fabrication at Haringhata, followed by wafer dicing and ATMP packaging.
Delivery & Testing
Receive packaged silicon samples and test boards with full access to INDNIX characterization lab.
Semiconductor Startup Registration
Apply for MPW shuttle runs, PDK access, and direct fabrication facilities
World-Class Cleanroom & Characterization Toolset
Startups and academic researchers gain supervised access to industry-standard tools at the INDNIX Haringhata Mega-Fab, West Bengal.
Lithography & Patterning
Deep-UV (193nm/248nm) step-and-scan projection lithography, direct-write electron-beam (E-Beam) nanolithography, and automated spin-coater tracks.
Thin-Film Deposition
Thermal & Plasma-Enhanced ALD (Atomic Layer Deposition), PECVD, LPCVD furnaces for high-k dielectrics, and magnetron sputtering for metals.
Dry & Wet Etching
Deep Reactive Ion Etching (DRIE / Bosch process) for MEMS silicon through-vias, high-density ICP-RIE for GaN/SiC, and chemical wet benches.
Metrology & Inspection
Field-Emission SEM (FE-SEM) with EDX chemical mapping, High-Resolution XRD, Atomic Force Microscopy (AFM), and spectroscopic ellipsometry.
Startup & Academic Alliance FAQ
Does INDNIX take equity from startups participating in the fab access program?
No. INDNIX operates primarily as a commercial pure-play semiconductor foundry partner. Startups retain 100% equity and 100% ownership of their chip designs and patents. For select high-potential deeptech startups requiring venture funding, INDNIX’s strategic venture arm may offer optional co-investment, but it is strictly non-mandatory.
Can startups leverage government subsidies like MeitY DLI with INDNIX?
Yes. Startups approved under the India Semiconductor Mission (ISM) Design-Linked Incentive (DLI) or Chips to Startup (C2S) schemes can deploy their government fabrication subsidies directly toward INDNIX MPW shuttle runs and packaging services.
How can university students and PhD scholars access cleanroom slots?
Once the educational institution signs an MoU with INDNIX, the nominated Principal Investigator (PI) or Department Head schedules cleanroom tool hours via the INDNIX Academic Booking Portal. All scholars undergo mandatory cleanroom safety, chemical handling, and gowning certification prior to tool operation.
What is the typical turnaround time for an MPW shuttle run?
From the scheduled shuttle tape-in cut-off date to wafer fabrication, dicing, and initial sample packaging delivery, the standard turnaround is 8 to 12 weeks for 65nm/180nm CMOS nodes, and 10 to 14 weeks for GaN/SiC power wafers.
Ready to Build the Future of Indian Silicon?
Whether you are a fabless startup with a breakthrough architecture or a university department pioneering advanced materials, INDNIX is your commercial manufacturing launchpad.