Two Architectures, One Goal

Power MOSFETs are the workhorses of switch-mode power conversion, handling the rapid on-off switching that transforms voltage levels with high efficiency. Two fundamental gate architectures dominate the market: planar and trench. Each has distinct manufacturing processes, electrical characteristics, and application sweet spots. Understanding the manufacturing perspective helps engineers make informed technology selections.

At INDNIX Technology, our power device fabrication facility produces both planar and trench MOSFETs, giving us unique insight into the tradeoffs between these architectures from a manufacturing standpoint.

Planar MOSFET Architecture

In a planar MOSFET, the gate electrode sits on top of the silicon surface. The channel forms horizontally along the surface beneath the gate oxide. Current flows vertically through the drain drift region but must make a 90-degree turn at the surface to flow horizontally through the channel.

Planar Manufacturing Process

The planar MOSFET process is relatively straightforward:

1. Grow or deposit gate oxide on the silicon surface
2. Deposit and pattern polysilicon gate electrode
3. Implant source and body regions using the gate as a self-aligned mask
4. Drive-in diffusion to form the channel
5. Deposit interlayer dielectric and open contact windows
6. Deposit and pattern source metallization

This process requires approximately 6 to 8 mask levels and uses well-established process steps. Yield is generally high because the critical dimension (gate length) is defined by a single lithographic step with relaxed tolerances (typically 1 to 5 micrometers).

Planar Limitations

The fundamental limitation of the planar architecture is cell pitch. The channel and source regions occupy significant lateral area, limiting the number of MOSFET cells that can be packed into a given die area. Fewer cells means higher total on-resistance for a given die size.

Additionally, the JFET resistance — the resistance of the narrow region between adjacent body diffusions — becomes a significant component of total on-resistance at higher voltages where the drift region must be thicker.

Trench MOSFET Architecture

In a trench MOSFET, the gate electrode is placed inside a trench etched into the silicon surface. The channel forms vertically along the trench sidewall, eliminating the need for lateral current flow through a surface channel. This vertical channel enables much denser cell packing and eliminates JFET resistance entirely.

Trench Manufacturing Process

The trench MOSFET process adds significant complexity:

1. Etch trenches into the silicon surface (typically 1 to 3 micrometers deep, 0.3 to 1.0 micrometer wide)
2. Grow gate oxide on the trench sidewalls and bottom (requires excellent uniformity on non-planar surfaces)
3. Fill the trench with polysilicon gate material
4. Planarize the polysilicon to the silicon surface
5. Implant source and body regions
6. Deposit interlayer dielectric and open contact windows
7. Deposit and pattern source metallization

This process requires 8 to 12 mask levels and introduces several challenging process steps that do not exist in planar fabrication.

Trench Process Challenges

Trench Etch Profile: The trench sidewall profile must be precisely controlled — typically 85 to 88 degrees from horizontal. Too vertical (approaching 90 degrees) creates voiding during polysilicon fill; too tapered wastes silicon area. Dry etching with chlorine-based chemistries provides the necessary profile control.

Corner Rounding: Sharp corners at the trench bottom concentrate electric fields, reducing breakdown voltage and degrading gate oxide reliability. Our trench process includes a sacrificial oxidation step that preferentially oxidizes sharp corners, creating a rounded profile that reduces the peak electric field by 30 to 50 percent.

Gate Oxide on Trench Sidewalls: Growing uniform, high-quality gate oxide on the vertical trench sidewall is more challenging than on a planar surface. Crystal orientation varies along the trench perimeter (the sidewall is typically on the [110] crystal plane while the surface is [100]), causing orientation-dependent oxidation rate and oxide quality differences. Our oxidation recipe is optimized to produce consistent oxide thickness and interface quality on both planes.

Polysilicon Fill: Completely filling a high-aspect-ratio trench with polysilicon without creating voids or seams requires careful control of deposition temperature, pressure, and silane flow rate. Voids in the polysilicon gate cause localized gate oxide stress and reliability degradation.

Performance Comparison

Parameter	Planar MOSFET	Trench MOSFET
Specific On-Resistance	Higher (more area per cell)	30-50% lower
Gate Charge (Qg)	Lower (smaller gate area)	Higher (trench sidewall area)
Figure of Merit (Rds·Qg)	Moderate	Better at low voltage
Avalanche Ruggedness	Generally superior	Requires careful design
Gate Oxide Reliability	Mature, well-understood	Requires corner rounding
Process Complexity	Lower (6-8 masks)	Higher (8-12 masks)
Manufacturing Cost	Lower	15-25% higher

Application-Driven Selection

Trench preferred for low-voltage applications (below 100V) where on-resistance dominance makes cell density paramount. Examples: DC-DC converters, battery switches, motor drivers for consumer electronics.

Planar preferred for high-voltage applications (above 200V) where avalanche ruggedness and gate oxide reliability are critical. Examples: industrial motor drives, automotive ignition, telecom power supplies.

Conclusion

The choice between trench and planar MOSFET architectures is fundamentally a manufacturing tradeoff between process complexity and device performance. Trench MOSFETs offer lower on-resistance at the cost of more complex fabrication, while planar MOSFETs provide manufacturing simplicity and robust reliability. At INDNIX Technology, our ability to fabricate both architectures allows us to recommend the optimal technology for each customer's specific voltage, current, and reliability requirements.