The Analog Computing Renaissance

For decades, the semiconductor industry has been dominated by digital computing — translating every problem into sequences of ones and zeros processed by ever-faster digital logic. But the energy cost of digital computing is becoming unsustainable for many emerging applications, particularly AI inference at the network edge where power budgets are measured in milliwatts, not watts.

Analog computing — performing mathematical operations directly on continuous signals without digitization — is experiencing a remarkable resurgence as a solution to the energy wall facing digital AI. At INDNIX Technology, our analog design group is developing analog processing circuits that perform neural network inference at 100 to 1,000 times lower energy than equivalent digital implementations.

Why Analog for AI?

The fundamental operation in neural network inference is the multiply-accumulate (MAC): multiplying an input activation by a weight and accumulating the result. A modern AI model like MobileNet requires approximately 600 million MACs per inference.

In a digital processor, each MAC requires:

• Reading the weight from memory (energy-dominant step)
• Reading the activation from memory
• Performing digital multiplication (multiple clock cycles for 8-bit or higher precision)
• Accumulating the result
• Writing the result back to memory

Total energy: approximately 1 to 10 picojoules per MAC operation.

In an analog processor, the MAC can be performed by:

• Applying the input activation as a voltage on a word line
• Storing the weight as a conductance in a non-volatile memory element (memristor, flash cell, or RRAM)
• Ohm's law (V × G = I) performs the multiplication intrinsically
• Kirchhoff's current law sums the currents from multiple rows, performing accumulation for free

Total energy: approximately 10 to 100 femtojoules per MAC — 100x to 1,000x improvement.

Analog AI Circuit Architectures

Crossbar Arrays

The most promising analog AI architecture uses crossbar arrays of non-volatile memory elements. Each memory element stores one neural network weight as a programmable conductance. Input activations are applied as voltages on the rows, and the resulting column currents represent the dot-product outputs.

A 256×256 crossbar array performs 65,536 MAC operations simultaneously in a single read cycle — massive parallelism that digital architectures cannot match at comparable energy budgets.

Analog-Domain Activation Functions

The ReLU (Rectified Linear Unit) activation function — the most common nonlinearity in neural networks — can be implemented trivially in analog: a simple diode or MOSFET operating in its threshold region provides the required clipping at zero. This eliminates the ADC-digital computation-DAC round trip that would otherwise be needed between layers.

Mixed-Signal Periphery

Practical analog AI accelerators use analog computation in the core MAC arrays with digital periphery for:

• Input DACs (converting digital activations to analog voltages)
• Output ADCs (converting analog results back to digital for inter-layer data movement)
• Digital control logic for memory programming and array selection

The precision requirements for these DACs and ADCs are relaxed (4 to 8 bits) because neural networks are inherently tolerant of quantization noise.

Challenges and Our Solutions

Device Variability

Analog computation is only as accurate as the analog components are matched. Transistor threshold voltage variations, resistor mismatches, and memory element conductance drift all introduce computational errors. Our analog process technology achieves transistor matching below 3 mV·μm (AVt) and resistor matching below 0.1 percent·√μm² — sufficient for 6 to 8 bit inference accuracy.

Noise

Thermal noise and flicker noise in analog circuits set a fundamental floor on computational precision. For a crossbar column sensing a current sum from 256 rows, the SNR must exceed approximately 35 dB to achieve 6-bit inference accuracy. Our low-noise column sense amplifiers achieve input-referred noise below 50 nV/√Hz, providing adequate SNR for 256-row crossbar operation.

Programming Precision

Non-volatile memory elements must be programmed to precise conductance values representing neural network weights. Our write-verify programming algorithm iteratively adjusts each element's conductance until it falls within the target window, achieving weight precision equivalent to 6 bits across the full conductance range.

Conclusion

Analog processing is re-emerging as a transformative approach to AI inference at the edge, offering 100x to 1,000x energy efficiency improvement over digital alternatives. At INDNIX Technology, our analog design expertise and precision fabrication capabilities are ideally suited to this renaissance, enabling ultra-low-power AI accelerators for IoT sensors, wearable health monitors, and autonomous edge devices that must operate for years on a single battery.