The Noise Floor: Analog's Fundamental Enemy

As supply voltages in modern semiconductor processes continue to decrease — from 5V in older nodes to 1.8V, 1.2V, 0.9V, and even 0.6V in advanced nodes — designing low-noise analog circuits becomes exponentially more difficult. The available signal swing shrinks with supply voltage, while many noise mechanisms remain constant or even worsen, degrading the achievable signal-to-noise ratio (SNR).

At INDNIX Technology, our analog design team specializes in ultra-low-voltage, low-noise circuit techniques that maintain precision signal processing capability even at supply voltages below 1 volt.

Noise Sources in Analog Circuits

Thermal Noise (Johnson-Nyquist Noise)

Every resistor and every transistor channel generates thermal noise proportional to absolute temperature and bandwidth. The thermal noise voltage spectral density of a resistor is given by 4kTR V²/Hz. At room temperature, a 10 kilohm resistor generates approximately 13 nV/√Hz of noise.

For MOSFET transistors, the drain current thermal noise is proportional to gm (transconductance). Increasing gm by increasing device width or bias current reduces the input-referred thermal noise — but at the cost of increased power consumption and parasitic capacitance.

Flicker Noise (1/f Noise)

Flicker noise, with a spectral density that increases inversely with frequency, dominates at low frequencies (below approximately 1 kHz to 1 MHz depending on device size and technology). Flicker noise is caused by charge carrier trapping and release at the silicon-oxide interface and is particularly problematic for sensor interface circuits that process quasi-DC physiological or environmental signals.

Flicker noise is inversely proportional to gate area (WL). Our design methodology uses physically large input transistors (gate areas exceeding 1,000 square micrometers) for critical low-noise front-end amplifiers, despite the increased parasitic capacitance, because the noise reduction is paramount.

Power Supply Noise

Digital switching activity on shared power supply rails generates broadband noise that couples into analog circuits through finite power supply rejection ratio (PSRR). At ultra-low supply voltages, the available PSRR headroom decreases because cascode and regulated cascode current sources — which provide excellent supply rejection in higher-voltage designs — cannot be stacked when the total supply voltage is only 0.9V.

Low-Voltage Circuit Techniques

Chopper Stabilization

Chopper amplifiers modulate the input signal to a higher frequency (above the 1/f noise corner), amplify it, and then demodulate it back to baseband. This effectively eliminates flicker noise and offset, but introduces chopping artifacts (ripple) at the chopping frequency that must be filtered. Our chopper amplifiers achieve input-referred offset below 1 microvolt and 1/f noise corner frequencies below 0.1 Hz at supply voltages of 1.2V.

Auto-Zeroing

Auto-zeroing techniques sample the amplifier offset during a calibration phase and subtract it during the signal processing phase. Correlated double sampling (CDS) is a common auto-zeroing technique used in switched-capacitor circuits. Unlike chopping, auto-zeroing introduces no ripple but doubles the wideband noise (by aliasing the noise from the calibration phase).

Bulk-Driven Transistors

At supply voltages below 1V, conventional gate-driven MOSFET amplifiers struggle because the threshold voltage (0.3 to 0.5V for standard-Vt devices) consumes a large fraction of the available supply headroom. Bulk-driven amplifiers use the substrate terminal as the signal input, bypassing the threshold voltage limitation. While bulk-driven transconductance is approximately 3 to 5 times lower than gate-driven transconductance for the same device, it enables rail-to-rail input common-mode range at supply voltages as low as 0.5V.

Subthreshold Operation

Operating transistors in the subthreshold (weak inversion) region maximizes transconductance-to-current ratio (gm/ID), which directly determines the noise-to-power tradeoff. In subthreshold, gm/ID approaches its theoretical maximum of approximately 25 V⁻¹ at room temperature (compared to 5 to 15 V⁻¹ in strong inversion), enabling the lowest possible noise for a given power budget.

Our ultra-low-power analog process includes transistor models validated in subthreshold operation, with accurate noise models extending to drain currents below 1 nanoampere.

Process Technology Support

Our analog process technology includes features specifically optimized for low-noise performance:

• Low-noise PMOS transistors with buried channel implants that separate the channel from the noisy Si-SiO₂ interface, reducing 1/f noise by 10x compared to surface-channel devices
• High-resistivity polysilicon resistors with sheet resistance of 1 to 10 kilohms per square, enabling high-value resistors in compact area for low-noise biasing networks
• Deep N-well isolation providing 60+ dB of substrate noise isolation between digital and analog sections
• Guard ring structures around sensitive analog blocks to intercept minority carrier injection from nearby digital switching

Conclusion

Managing noise in ultra-low voltage analog circuits requires a comprehensive approach spanning circuit architecture (chopping, auto-zeroing), device-level optimization (bulk-driven, subthreshold), and process technology features (buried channels, deep isolation). At INDNIX Technology, our analog design and process teams work in concert to deliver precision analog circuits that maintain microvolt-level noise performance even at sub-1V supply voltages — enabling the next generation of battery-powered medical, IoT, and wearable devices.